1. Field of the Invention
The present invention relates to process apparatuses, and more particularly to cluster processing apparatuses for semiconductor wafers.
2. Description of the Related Art
With advances in electronic products, semiconductor technology has been applied widely in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emitting diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high integration and speed requirements, dimensions of semiconductor integrated circuits have been reduced and various materials, such as copper and ultra low-k dielectrics, have been used along with techniques for overcoming manufacturing obstacles associated with these materials and requirements.
FIG. 1 is a schematic cross-sectional drawing showing a traditional via hole structure. A copper layer 110 is formed over a substrate 100. A low-k dielectric layer 120 is formed over the copper layer 110. A copper via 130 is formed within the low-k dielectric layer 120. If the copper via 130 is exposed to air, the top surface of the copper via 130 reacts with oxygen in air, forming a copper oxide layer 140 due to oxidation. The copper oxide layer 140 can adversely affect the electrical connection between the top surface of the copper via 130 and a conductive layer (not shown) formed thereover. Accordingly, great care should be taken to avoid exposure to air during critical process steps, such as via opening, formation of copper seed layers, formation of copper layers, copper chemical mechanical polish (CMP) and formation of the ultra low-k dielectric material.
Traditionally, after a critical process step, the substrate 100 is removed from the process chamber that performs the critical process step and temporarily stored in a cassette or front opening unified pod (FOUP) until subsequent processing. When the door of the cassette or FOUP is removed to allow placement of the substrate 100 in the cassette or FOUP, air from the surrounding environment including oxygen flows into the cassette or FOUP. After the door is closed, the air is sealed within the cassette or FOUP with the substrate 100. As described above, oxygen tends to react with the copper layer 110 formed over the substrate 100 to form the copper oxide layer 140.
In order to address this problem, a “Q-time” is required after a critical process step is performed in the semiconductor manufacturing process. The next substrate process must be performed within a set predetermined time period or Q-time, such as from 2 to 4 hours. If a subsequent process, such as formation of a barrier layer, does not occur within the time period, a cleaning process is required to remove any copper oxide layer 140 formed over the copper layer 110.
Due to the high integration of semiconductor devices over substrate 100, a semiconductor process usually has a plurality of the critical steps each with an associated Q-time designed to protect the substrate. These Q-time requirements complicate the manufacturing processes. In addition, if a Q-time is missed, the required additional steps, such as for cleaning, increase process time and complexity.
By way of background, U.S. Patent Publication No. 2002/0074664 to Nogami et al. provides a description of a semiconductor manufacturing method, the entirety of which is hereby incorporated by reference herein. In this reference, a CoWP (cobalt tungsten phosphor) film is formed over a copper layer to prevent oxidation of the exposed copper layer. However, after the formation of the copper layer and before the formation of the CoWP film, the substrate including the copper layer is moved from the process chamber and exposed to the environment. A copper oxide layer forms over the copper layer before the formation of the CoWP film. The method of Nogami et al., therefore, cannot completely protect the copper layer from oxide formation.
From the foregoing, improved process apparatuses and methods are desired.